1. Technical Field
The present disclosure relates to a non-volatile memory device and, more specifically, to a method for programming a multi-level non-volatile memory device.
2. Description of the Related Art
Flash memory is a form of computer memory that can retain data without having to consume power and is thus characterized as non-volatile. Flash memory may be programmed and erased in blocks.
Flash memory stores data in an array of floating gate transistors called cells. In single-level flash memory, one bit of data may be stored in each cell. In multi-level flash memory, more than one bit of data may be stored in each cell by differentiating between several levels of charge that may be stored in the floating gate of the cell.
FIG. 1 is a schematic diagram showing a single cell 10 of flash memory. Flash memory is comprised of a p-type semiconductor substrate 11 that may be doped, for example, with boron ions. An n-type source region 12 and an n-type drain region 13 may be formed within the substrate 11 by doping, for example, with phosphorus, arsenic, or antimony ions. A floating gate 14 may be formed above the substrate 11 and may be insulated from the substrate. A control gate 15 may be formed above the floating gate 14 and may be insulated from the floating gate 14. Because the floating gate 14 is completely insulated, charge that may be stored within the floating gate is trapped and thus data may persist in the floating gate without the consumption of electricity.
Flash memory may be either NOR memory or NAND memory. Each form of flash memory has its own set of characteristics. For example, NOR flash utilizes a process called hot electron injection to trap charge within the floating gate and relies on quantum tunneling to discharge the floating gate. NAND flash utilizes quantum tunneling both to trap charge and discharge.
A NAND flash memory device may be organized into strings. FIG. 2 shows an example of a string of NAND flash memory. The illustrated string is depicted physically 200A and in terms of its analogous electrical schematic 200B. Each string is a group of cells connected in series. Bach string may comprise, for example, 16 or 32 cells. Each string may have a bit line with a bit line contact 210 and one or more gates for controlling the string. For example, each string may have a select gate 220 and a control gate 230. The string may also have a floating gate 240 and a cell source line 250.
Multiple strings may be connected to form a page. Word lines may connect analogous cells in each string of the page. Multiple pages may be organized into blocks. FIG. 3 shows an example of a flash memory block. The flash memory 100 has an X-Decoder 130 that controls voltages of the word lines (WL), the string select line (SSL) and the ground selection line (GSL). The flash memory 100 also has a page buffer circuit 150 for controlling voltages of the bit lines (BL). The flash memory 100 is organized as a block 110 made up of strings. In FIG 3, strings 110_1, 110_2, and 110_M are shown, however, it is to be understood that there may be any number of strings between 110_2 and 110_M. Here, string 110_1 has a bit line “BLe” and string 110_2 has a bit line “BLo”. The flash memory 100 is also organized into pages. An example of a page is shown as 110p. 
Each string may be connected to a string selection line (SSL), a ground selection line (GSL), a series of word lines (WL) numbered WL<N-1> through WL<0>, and a common source line (CSL), and each string may have a string selection transistor (SST), a ground select transistor (GST) and a series of memory cell transistors (MCT) numbered MCT<N-1> through MCT<0>.
In the flash memory device, the presence and degree of charge within the floating gate affects the threshold voltage of the cell. The threshold voltage of the cell may be understood to be the minimum voltage that need be applied to the control gate before current may begin to flow between the source and drain. Accordingly, the cell may be read by applying a predetermined voltage to the control gate and determining whether current may flow between the source and drain. In practice sense amplifiers may be used to detect and amplify observed current flow.
In a multi-level flash, multiple discrete levels of charge may be stored within the floating gate of the cell. For example, in a 2-bit multi-level flash, there may be four discrete levels of charge that may be stored within the floating gate of the cell. In this case, the cell may exhibit one of four distinct threshold voltages depending on the level of charge trapped in the floating gate. The level of charge stored in the cell, and hence the stored data value, may he determined by applying a test voltage to the control gate and determining whether current flows. For a 2-bit multi-level flash, it may be necessary to test whether current flows at up to 3 discrete read voltages to determine the state of the cell.
Multi-level flash may have more than 2-bits. For example, a multi-level flash may have 3 or more bits. A 3-bit flash would have 8 (23) states per cell, a 4-bit flash would have 16 (24) states per cell, a 5-bit flash would have 32 (25) states per cell, etc. The operative threshold levels of such multi-level flash would have to be set over the range of possible values and adjacent threshold ranges may be separated by margins. Accordingly, flash having higher number of bits must be able to set charge levels within narrower ranges and have narrower margins. To accommodate these narrower ranges and margins, charge must be added to cells with increased precision. The process of adding charge to cells is referred to as “programming.” Accordingly, programming for multi-level flash memory requires increased precision.
When programming flash memory, particularly multi-level flash with increased precision, it is possible that the programming operation may be interrupted. For example, power may be lost or the flash memory device may be prematurely disconnected. Under these circumstances, it is possible that, data previously written to the flash memory may become unreadable. Accordingly, programming for flash memory, particularly multi-level flash memory may carry a risk of memory loss.